In general, a digital circuit is designed based on a function specification and RTL description, i.e., description of a register transfer level (RTL), or the like is formed. Logic synthesis constraint conditions in consideration of a timing constraint are also formed based on the function specification. The RTL description and the logic synthesis constraint conditions are input to a logic synthesis tool to generate a netlist at a gate level satisfying the timing constraint (timing specification).
The logic synthesis constraint conditions include, as a timing exception, a multicycle path specification indicating that a signal propagation path from an output terminal of one of a pair of flipflops connected without any flipflop interposed therebetween to an input terminal of the other one of the flipflops is a propagation path allowed to require a plurality of clock cycles for signal propagation. The logic synthesis constraint conditions also include a condition (which will be hereafter referred to as “multicycle number”) indicating a maximum amount of time, i.e., the largest number of clock cycles is allowed for signal propagation on each multicycle path. In the logic synthesis tool, if the above-described multicycle path specification (or a timing exception specification such as a false path specification) is not included, logic synthesis is performed such that signal propagation between sequential circuits is counted as 1 cycle. On the other hand, if the multicycle path specification is included, logic synthesis is performed for a specified path such that an amount of time required for signal propagation is smaller than a specified multicycle number.
Normally, the above-described logic synthesis constraint conditions for the multicycle path are manually obtained based on a functional specification. Therefore, logic synthesis is frequently performed using incorrect conditions. In such a case, a generated logic circuit might not be properly operated or, even if a generated logic circuit is properly operated, a circuit size might be increased because of excessive timing adjustment.
To cope with the above-described situations, there has been a proposed method in which a delay information is buried in RTL description and validation is performed by analyzing the delay information to extract a multicycle path candidate and running the multicycle path candidate against a separately generated multicycle path specification (see, for example, Patent Reference 1).
Moreover, a technique in which a target circuit is analyzed, for example, in response to the name of each device, the meaning of a signal to a terminal or the relationship thereof and a multicycle path is automatically detected has been proposed (see, for example, Patent Reference 2).    Patent Reference 1: Japanese Laid-Open Publication No. 2001-273351    Patent Reference 2: Japanese Laid-Open Publication No. 2004-171149